A programmable gate array (PGA) is a general purpose programmable logic device that is customizable by an end user. A PGA typically includes of an array of configuration memory cells for storing data that defines the operation of the PGA. The configuration memory cells are typically static random access memory (SRAM) cells.
PGAs generally include an array of logic elements that are arranged in rows and columns. Each logic element of a tile based SRAM PGA includes a configurable logic block, a programmable routing matrix, and a group of configuration memory cells associated with it. Each configurable logic block may perform any one of a variety of logic functions. The logic function performed by a particular logic block is defined by configuration data stored in its associated group of configuration memory cells. The programmable routing matrix allows the inputs and outputs of the logic block to be coupled to the inputs and outputs of other logic blocks or the inputs and outputs of the PGA. The couplings of the inputs and outputs of a particular logic block are similarly defined by data stored in its associated group of configuration memory cells. The programmable routing matrix, along with metal signal lines that may be connected with the routing matrix, interconnect the logic blocks of the PGA.
The output of each memory cell may be set either high or low by storing a corresponding bit in the memory cell. Storing configuration data in the memory cells of the PGA is called "configuring" the PGA. The data stored in the memory cells may be changed, or re-configured, to modify the function of the PGA.
The memory cells of the PGA are arranged as an array of cells in columns and rows. The PGA typically provides a single address register and a single data register for loading configuration data into the memory cells. The data register is typically a serial input shift register.
As semiconductor technology advances, additional chip space is available for greater numbers of logic elements as well as logic blocks having more programmable functions. In spite of the trend toward more available chip space, chip space remains a resource to be conserved. Smaller chips are cheaper to produce and operate faster. PGA chip space needs to be conserved because new functionality and capability will most often fully utilize the available chip space. Therefore, it would be desirable to have a PGA architecture that reduces usage of chip space while maintaining present capabilities and functionality.